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LCP1521
PROGRAMMABLE TRANSIENT VOLTAGE SUPPRESSOR FOR SLIC PROTECTION
Application Specific Discretes A.S.D.TM
FEATURES Dual programmable transient suppressor Wide negative firing voltage range: VMGL = -150 V max. Low dynamic switching voltages: VFP and VDGL Low gate triggering current: IGT = 2 mA max Peak pulse current: IPP = 30 A (10/1000 s) Holding current: IH = 150 mA
SO-8 DESCRIPTION This device has been especially designed to protect new high voltage, as well as classical SLICs, against transient overvoltages. Positive overvoltages are clipped with 2 diodes. Negative surges are suppressed by 2 thyristors, their breakdown voltage being referenced to -VBAT through the gate. This component presents a very low gate triggering current (IGT) in order to reduce the current consumption on printed circuit board during the firing phase. A particular attention has been given to the internal wire bonding. The Kelvin method configuration ensures reliable protection, reducing the overvoltage introduced by the parasitic inductances of the wiring L x(dI/dt), especially for very fast transients.
FUNCTIONAL DIAGRAM
TIP
TIP
GATE
GND
NC
GND
RING
RING
September 1999 - Ed: 2A
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COMPLIES WITH THE FOLLOWING STANDARDS: ITU-T K20 VDE0433 VDE0878 IEC1000-4-5 FCC Part 68 lightning surge type A FCC Part 68 lightning surge type B BELLCORE: NWT-001089-CORE First level BELLCORE: NWT-001089-CORE Second level Peak Surge Voltage (V) 4000 1000 2000 2000 level 3 level 4 1500 800 1000 2500 1000 5000 Voltage Waveform (s) 10/700 10/700 10/700 1.2/50 10/700 1.2/50 10/160 10/560 9/720 2/10 10/1000 2/10 Current Waveform (s) 5/310 5/310 5/310 1/20 5/310 8/20 10/160 10/560 5/320 2/10 10/1000 2/10 Admissible Ipp (A) 40 25 40 50 40 100 50 35 25 170 30 170 Necessary Resistor () 60 10 2 10 22 15 10 24 20
Note 1: the mentioned value of the series resistance is the minimum value needed to fulfill the standard requirement.
ABSOLUTE MAXIMUM RATINGS (Tamb = 25C, unless otherwise specified). Symbol IPP Parameter
Peak pulse current (see note1)
Value 10/1000s 5/310s 2/10s tp = 10ms t = 1s
-40C < Tamb < +85C -40C < Tamb < +85C
Unit A
30 40 170 20 5 2 -150 -150 - 55 to + 150 150 260
ITSM IGSM VMLG VMGL Tstg Tj TL
Non repetitive surge peak on-state current (F = 50Hz) Maximum gate current (half sine wave tp = 10ms) Maximum voltage LINE/GND Maximum voltage GATE/LINE Storage temperature range Maximum junction temperature Maximum lead temperature for soldering during 10s
A A V C C
Note 1: Pulse waveform 10 / 1000 s 5 / 310 s 2 / 10 s
tr = 10 s tr = 5 s tr = 2 s
tp = 1000 s tp = 310 s tp = 10 s
% IPP
100 50 0 tr tp
t
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THERMAL RESISTANCE Symbol Rth (j-a)
Junction to ambient
Parameter
Value 170
Unit C/W
ELECTRICAL CHARACTERISTICS (Tamb = 25C) Symbol IGT IH IRM IRG VRM VGT VF VFP VDGL VGATE VRG C Parameter
Gate triggering current Holding current Reverse leakage current LINE / GND Reverse leakage current GATE / LINE Reverse voltage LINE / GND Gate triggering voltage Forward drop voltage LINE / GND Peak forward voltage LINE / GND Dynamic switching voltage GATE / LINE GATE / GND voltage Reverse voltage GATE / LINE Capacitance LINE / GND
IPP VDGL VR VRM VF IRM IR IH
1 - PARAMETERS RELATED TO THE DIODE LINE / GND (Tamb = 25C) Symbol VF VFP (note 1) Test conditions
Square pulse : tp = 500s 10/700s 1.2/50s 2/10s IF = 5A RP = 10 RP = 10 RP = 62
Max 2 5 7 12
Unit V V
1.5kV 1.5kV 2.5kV
Note 1: see test circuit for VFP; RP is the protection resistor located on the line card.
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2 - PARAMETERS RELATED TO THE PROTECTION THYRISTOR (Tamb = 25C) Symbol IGT IH VGT IRG VDGL Test conditions
VGND / LINE = -48V VGATE = -48V (see note 2) at IGT Tc=25C Tc=85C VRG = -150V VRG = -150V
Min 0.1 150
Max 2
Unit mA mA
1.5 5 50
V A
VGATE = -48V (see note 3) 10/700s 1.2/50s 2/10s 1kV 1.5kV 2.5kV RP = 10 RP = 10 RP = 62 IPP = 30A IPP = 30A IPP = 38A
7 10 25
V
Note 2: see functional holding current (IH) test circuit Note 3: see test circuit for VDGL The oscillations with a time duration lower than 50ns are not taken into account
3 - PARAMETERS RELATED TO DIODE AND PROTECTION THYRISTOR (Tamb = 25C) Symbol IRM C
Tc=25C Tc=85C
Test conditions
VGATE / LINE = -1V VGATE / LINE = -1V VRM = -150V VRM = -150V
Max 5 50 100 50
Unit A pF
VR = -3V F = 1MHz VR = -48V F = 1MHz
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FUNCTIONAL HOLDING CURRENT (IH) TEST CIRCUIT : GO-NO GO TEST
R - VP VBAT = - 100 V
D.U.T.
Surge generator
This is a GO-NO GO test which allows to confirm the holding current (IH) level in a functional test circuit. TEST PROCEDURE : - Adjust the current level at the IH value by short circuiting the D.U.T. - Fire the D.U.T. with a surge current : IPP = 10A, 10/1000s. - The D.U.T. will come back to the off-state within a duration of 50ms max.
TEST CIRCUIT FOR VFP AND VDGL PARAMETERS
(V is defined in unload condition)
P
R4 TIP R2 RING R3
L
VP
C1
R1
C2
G ND
Pulse (s) tr 10 1.2 2 tp 700 50 10
Vp (V) 1500 1500 2500
C1 (F) 20 1 10
C2 (nF) 200 33 0
L (H) 0 0 1.1
R1 () 50 76 1.3
R2 () 15 13 0
R3 () 25 25 3
R4 () 25 25 3
IPP (A) 30 30 38
Rp () 10 10 62
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TECHNICAL INFORMATION Fig. A1: LCP1521 concept behavior.
Rs1
L1
TIP IG ID1 T1 Gate Th1 D1 GND
V Tip
GND
-Vbat
C
Rs2
RING
L2 V Ring
Figure A1 shows the classical protection circuit using the LCP1521 crowbar concept. This topology has been developed to protect the new high voltage SLIC's, it allows to program the negative firing threshold while the positive clamping value is fixed at GND. When a negative surge occurs on one wire (L1 for example) a current Ign flows through the base of the transistor T1 and then injects a current in the gate of the thyristor Th1. Th1 fires and all the surge current flows through the ground. After the surge when the current flowing through Th1 becomes less negative than the holding current IH, then Th1 switches off. When a positive surge occurs on one wire (L1 for example) the diode D1 conducts and the surge current flows through the ground. Fig. A2: Example of PCB layout based on LCP1521 protection.
220 nF
To the line side
GND
To the SLIC side
In order to minimize the remaining voltage across the SLIC inputs during the surge, the TIP and RING pins of the LCP1521 are doubled (Pins 1 and 8 for TIP / Pins 4 and 5 for RING). This fact allows the board designer to connect the track like designed in figure A2. With such a PCB design, the extra voltages caused by track stray inductance (LdI / dt) remain located on the line side of the LCP and do not affects its SLIC side. The capacitor C is used to speed up the crowbar structure firing during the fast surge edges. This allows to minimize the dynamical breakover voltage at the SLIC Tip and Ring inputs during fast strikes. Please note that this capacitor is generally present around the SLIC - Vbat pin. So to be efficient it has be as close as possible from the LCP1521 Gate pin and from the reference ground track (or plan) (see Fig. A2). The optimized value for C is 220nF.
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The series resitors Rs1 and Rs2 designed in figure 1 represent the fuse resistors or the PTC which are mandatory to withstand the power contact or the power inductance tests imposed by the different country standards. Taking into account this fact the actual lightning surge current flowing through the LCP is equal to: I surge = V surge / (Rg + Rs) With V surge = peak surge voltage imposed by the standard. Rg = series resistor of the surge generator Rs = series resistor of the line card (e.g. PTC)
e.g. For a line card with 30 of series resistors which has to be qualified under Bellcore 1000V 10/1000s surge, the actual current through the LCP1521 is equal to: I surge = 1000 / (10 + 30) = 25A The LCP1521 is particularly optimized for the new telecom applications such as the fiber in the loop, the WLL, the decentralized central office for example. These short line applications need smaller operating voltages than the long line applications and then allow the use of high voltage SLIC's operating without ring relay. The schematics of figure A3 gives the most frequent topology used for these emergent applications.
Fig. A3: Protection of high voltage SLIC.
-Vbat Rs (*) TIP Gate TIP GND GND RING Rs (*) RING
Line
GND
220nF
SLIC
LCP1521 Line card
Rs (*) = PTC or Resitor fuse
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Surge peak current versus overload duration. Relative variation of holding current versus junction temperature
ITSM (A) 20 18 16 14 12 10 8 6 4 2 0 0.01
IH [Tj] / IH [Tj=25C] 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -40
t(s) 0.1 1 10 100 1000
Tj(C) -20 0 20 40 60 80 100
ORDER CODE
LCP
LINE CARD PROTECTION
15
IH = 150 mA
2
1
PACKAGE 1 : SO-8
RL
VERSION
RL : Tape & Reel : Tube
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PACKAGE MECHANICAL DATA SO-8 (Plastic) DIMENSIONS REF.
L c1 C a3 a2 A b1
Millimetres Min. Typ. Max. Min. 1.75 0.1 0.65 0.35 0.19 0.25 4.8 5.8 1.27 3.81 3.8 0.4 4.0 0.15 1.27 0.016 0.6 8 (max) 0.50 0.25 0.004 1.65 0.85 0.025 0.48 0.014 0.25 0.007 0.50 0.010 45 (typ) 5.0 6.2 0.189 0.228
Inches Typ. Max. 0.069 0.010 0.065 0.033 0.019 0.010 0.020 0.197 0.244 0.050 0.150 0.157 0.050 0.024
A a1 a2 a3 b b1 C c1 D
b e3
e
S
E
a1
D M
8
5 F
E e e3 F L M S
1
4
Order code LCP1521 LCP1521RL
Marking 151DHV 151DHV
Package SO-8 SO-8
Weight 0.08 g 0.08 g
Base qty 2500 2000
Delivery mode Tube Tape & Reel
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics (c) 1999 STMicroelectronics - Printed in Italy - All rights reserved. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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